The “Beyond Moore” Era: Pushing the Boundaries of Semiconductors
In the past, the technological advancement in the world of semiconductors revolved around who could make smaller transistors and fit more on a single chip. Gordon Moore predicted that the density of transistors on a chip doubles every 24 months — the famous “Moore’s Law”. Although it has gone through some adjustments over history to reflect the speed of technological growth, “Moore’s Law” has been considered the fundamental principle of semiconductor technology development for the last five decades.
Today’s era of smartphones, mobile internet, AI and big data calls for increasingly faster speeds of computing performance. However, the speed of semiconductor innovation and technology advancement has slowed down, and chip miniaturization has reached physical limits, which has caused the speed at which transistors are growing smaller to slow down. In other words, we are now falling behind Moore’s Law.
The market also demands semiconductors to be versatile, encompassing a variety of features such as analog or RF wireless communication in one chip. But as the semiconductor process becomes increasingly miniaturized, it gets increasingly difficult to maintain analog performance. It is indeed becoming difficult to address the needs of the market just through process miniaturization based on Moore’s Law.
In order to overcome these limitations of semiconductor technology, an approach that goes beyond the existing Moore’s Law is required, and we call this “Beyond Moore”.
“Advanced Package, Leading the Beyond Moore Era”
Our answer to the Beyond Moore era is Advanced Package technology. Through advanced Heterogeneous Integration, which connects multiple chips horizontally and vertically, more transistors can be planted on a single chip (or package) and offer performance that is more powerful than the sum of all parts.
According to market research, the CAGR of the advanced packaging industry is estimated at 9.6% growth rate between 2021 and 2027. In fact, 2.5D1 and 3D packages2 implementing heterogeneous integration is expected to show an even higher growth rate of 14%.
Governments are also paying close attention. The South Korean Ministry of Trade, Industry and Energy hosted a forum on semiconductor packaging technology in February, while DARPA (Defense Advanced Research Projects Agency) of the US Department of Defense announced the allocation of a large-scale budget for advanced package-related fields last April. The Japanese government also announced new incentives to attract research centers, as well as establishing a dedicated symposium.
“One-Stop Advanced Package Solution with High Performance and Low Power”
In a bid to address the growing importance of advanced packaging technology, Samsung Electronics established the AVP (AdVanced Package) Business Team under the Device Solutions Division last December to boost the company’s capabilities in advanced packaging technology and maximize the synergy between business units.
Samsung Electronics, with industry-leading expertise in memory, logic foundry and package business, is well-positioned to utilize heterogeneous integration to offer competitive 2.5D and 3D packages that connect state-of-the-art logic semiconductors produced with EUV and high-performance memory semiconductors such as HBM.
The AVP Business Team operates under a business model that provides one-stop advanced package solutions that enable high-performance and low-power solutions. We communicate closely and directly with customers in order to provide solutions tailored to the needs of each customer and product. Our focus areas are the development of next-generation 2.5D and 3D advanced package solutions based on RDL,3 Si Interposer/Bridge4 and TSV5 stacking technologies.
“Our Future Beyond Connection”
The goal of the AVP Business Team is “hyper-connection” (or “hyper-integration”). “Hyper-connection” is more than a simple sum of the performance and functions of each semiconductor. We envision creating a greater synergy that connects semiconductors to the world, connects people to people and connects customers’ imaginations to reality.
Samsung Electronics is committed to a competitive development and production strategy, with proprietary packaging technology compatible with the large-area trend. Based on customer-oriented business development that ensures prompt responses to customer requests, the AVP Business Team will bring products of imagination to reality.
1 2.5D package: A package which integrates a single-layer logic semiconductor and multi-layer memory semiconductor together on a substrate
2 3D package: a package in which multiple logic/memory semiconductors are vertically integrated
3 RDL (Redistribution Layer): Advanced packaging technology that places an extra metal layer in between a small and large circuit board to integrate the two
4 Si Interposer/Bridge: The microcircuit board inserted between the IC chip and PCB, which physically connects the chip and board by acting as the mid-level wiring
5 TSV (Through Silicon Via): Advanced package technology that grinds the surface of the chip, drills hundreds of microscopic holes and connects the electrodes that vertically penetrate the holes in the top and bottom chips.
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